1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a memory array.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies known as EEPROM and flash memory based on charge storage are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising in memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, MONOS, TANOS and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride.
Conventionally, after the charge trapping dielectric layer is formed over the substrate, the word lines are formed by forming a conductive layer over the substrate and then patterning the conductive layer into the word lines. By using the method for forming the word lines mentioned above, it is difficult to further scale down the size of each of the word lines since the size of the word line is limiter by the resolution of the optical tool used in the photolithography process. Therefore, the size of a memory unit is limited by the capability of the photolithography process.